The present invention relates generally to the inspection of semiconductor integrated circuit (IC) chips and more particularly, to a method and system for establishing a common reference point on a semiconductor wafer inspected by two or more scanning mechanisms.
Integrated circuits (ICs) are commonly manufactured through a series of processing steps. Very often more than a hundred processing steps are performed to produce a properly functioning integrated circuit chip.
A semiconductor material, commonly in the shape of a wafer, serves as the substrate for integrated circuits. Semiconductor ICs are typically manufactured as an assembly of a hundred or more chips on a single semiconductor wafer, which is then cut up to produce the individual IC chips. Typically, a wafer made of silicon is used as the integrated circuit substrate, the silicon wafer being approximately 150-200 mm in diameter and 0.5-1 mm thick. During the manufacturing process, the silicon wafer is first polished and cleaned to remove all contaminant particles situated thereon. The silicon wafer is then treated in preparation for a series of processing steps involving a plurality of photolithographic patterns (also commonly referred to as masks). In the production of integrated circuits, microelectronic circuits are formed onto the silicon wafer through a process of layering. In the layering process, conductive and insulative layers of thin films are deposited and patterned onto the silicon wafer. Each layer is patterned by a mask designed specifically for it, the mask defining the areas within the wafer that are to be treated such as by etching or implanting.
Semiconductor fabrication technology today deals with silicon wafers which are approximately 200 mm in diameter and which feature geometries with dimensions well below 1 .mu.m (micrometer). Due to the high complexity and level of integration of integrated circuits, the absence of contaminants on every layer of the wafer is critical in order to realize acceptable levels of product yield. Specifically, the presence of one contaminant particle larger than the half the width of a conductive line on the silicon wafer can result in complete failure of a semiconductor chip produced from the wafer. Such a wafer has to be discarded which thereby decreases the percentage yield per wafer and increases the overall cost of the individual chips. Therefore, a critical task facing semiconductor process engineers is to identify and, as far as possible, to eliminate sources of surface contamination on each layer of the semiconductor wafer.
Accordingly, inspection systems are well known in the art and are commonly used to detect and analyze the presence of contaminant particles on semiconductor wafers at a variety of positions along the production line of the integrated circuit. Commercially available patterned wafer inspection systems include system model numbers TPC 8500 and TPC 9000 manufactured by Inspex, Inc. of Billerica, Mass. Such inspection systems typically include one or more inspection instruments (such as laser scanning tools) which detect and locate particles on the wafer.
As example of an inspection instrument commonly used to detect particles on a semiconductor wafer, U.S. Pat. No. 4,772,126 to C. D. Allemand et al discloses an apparatus and method for detecting the presence of particles on the surface of an object such the front side of a patterned semiconductor wafer. A vertically expanded, horizontally scanning, beam of light is directed onto an area on the surface of the object at a grazing angle of incidence. A video camera positioned above the surface detects light scattered from any particles which may be present on the surface, but not specularly reflected light. The surface is angularly prepositioned (rotated) relative to the incident light beam so that the diffracted light from the surface and the pattern of lines on the surface is at a minimum. The object is then moved translationally to expose another are to the incident light beam so that the entire surface of the object or selected portions thereof can be examined, an area at a time. It is well known in the art for inspection systems to include a plurality of different inspection instruments, each inspection instrument being responsible for inspecting the wafer at a particle point in time during the manufacturing process. As such, each inspection instrument will inspect the semiconductor wafer after the treatment of a particular layer of the integrated circuit. By using multiple inspection instruments to scan various layers of the semiconductor wafer for contaminant particles, the user is able to discern where, and more specifically on which layer, a defect first occurred in the manufacturing process. The ability to discern where a defect first occurred is extremely useful in removing the defect and in preventing future contamination.
However, in order to detect where in the manufacturing process a defect first occurred, it is necessary to compare the location of the defects detected by each inspection instrument used to inspect a particular layer of the wafer. To effectively perform the comparison, all of the inspection instruments must have a common coordinate system. A common coordinate system for all the inspection instruments will ensure that if a defect is carried over to subsequent layers, the defect will have exactly the same coordinates in each layer. Otherwise, the user would be unable to determine whether a defect has been carried over from a previous layer or whether, in fact, the defect is new.
To establish a common coordinate system, it is well known in the art to select a common point on the semiconductor wafer as the origin of the wafer for each of the various inspection instruments. The point selected to be the origin for all the inspection instruments is generally given a coordinate value of (0,0) by which all other points are assigned a coordinate value in relation thereto.
It is well known in the art to use the center of the wafer as the origin to establish a common coordinate system for multiple inspection instruments, wherein each particle detected in each layer is denoted a coordinate value relative to the common reference point, the center of the wafer.
One drawback of such a system is that the point determined to be the center of the wafer may vary or drift from scanning tool to scanning tool. This condition is commonly referred to as center of the wafer (COW) drifting between inspection mechanisms. As a result of the center of the wafer drifting between inspection instruments, the coordinate values assigned by one inspection instrument for various points on the semiconductor wafer will not coincide with the coordinate values assigned by another inspection instrument for the same points. Since the same defects will be assigned different coordinate values by different scanning tools, the user will be precluded from effectively determining on which layer the particle was introduced to the wafer.
In U.S. Pat. No. 5,267,017 to Y. S. Uritsky et al there is disclosed a method for reducing targeting errors encountered when trying to locate contaminant particles in a high-magnification imaging device, based on estimates of the particle positions obtained from a scanning device. The method of the invention uses three techniques separately and in combination. The first technique includes selecting at least three reference particles, to provide multiple unique pairs of reference particles for computation of an averaged set of coordinate transformation parameters, used to transform particle position coordinates from the coordinate system of the scanning device to the coordinate system of the imaging device. The averaged transformation parameters result in much smaller targeting errors between estimated and actual positions of the particles. The targeting errors are further reduced by the use of multiple scans of the scanning device. In a third technique, accumulated reference particle targeting errors observed in prior processing of other wafers are used to reduce these targeting errors when processing a new wafer.
Other patents of interest include U.S. Pat. No. 5,539,752 to A. Berezin et al, U.S. Pat. No. 5,422,724 to P. D. Kinney et al, and U.S. Pat. No. 5,280,437 to D. A. Corliss.